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Espressif Systems /ESP32-P4 /SPI0 /SPI_MEM_CACHE_FCTRL

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Interpret as SPI_MEM_CACHE_FCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_AXI_REQ_EN)SPI_MEM_AXI_REQ_EN 0 (SPI_MEM_CACHE_USR_ADDR_4BYTE)SPI_MEM_CACHE_USR_ADDR_4BYTE 0 (SPI_MEM_CACHE_FLASH_USR_CMD)SPI_MEM_CACHE_FLASH_USR_CMD 0 (SPI_MEM_FDIN_DUAL)SPI_MEM_FDIN_DUAL 0 (SPI_MEM_FDOUT_DUAL)SPI_MEM_FDOUT_DUAL 0 (SPI_MEM_FADDR_DUAL)SPI_MEM_FADDR_DUAL 0 (SPI_MEM_FDIN_QUAD)SPI_MEM_FDIN_QUAD 0 (SPI_MEM_FDOUT_QUAD)SPI_MEM_FDOUT_QUAD 0 (SPI_MEM_FADDR_QUAD)SPI_MEM_FADDR_QUAD 0 (SPI_SAME_AW_AR_ADDR_CHK_EN)SPI_SAME_AW_AR_ADDR_CHK_EN 0 (SPI_CLOSE_AXI_INF_EN)SPI_CLOSE_AXI_INF_EN

Description

SPI0 bit mode control register.

Fields

SPI_MEM_AXI_REQ_EN

For SPI0, AXI master access enable, 1: enable, 0:disable.
SPI_MEM_CACHE_USR_ADDR_4BYTE

For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
SPI_MEM_CACHE_FLASH_USR_CMD

For SPI0, cache read flash for user define command, 1: enable, 0:disable.
SPI_MEM_FDIN_DUAL

For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
SPI_MEM_FDOUT_DUAL

For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
SPI_MEM_FADDR_DUAL

For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
SPI_MEM_FDIN_QUAD

For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
SPI_MEM_FDOUT_QUAD

For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
SPI_MEM_FADDR_QUAD

For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
SPI_SAME_AW_AR_ADDR_CHK_EN

Set this bit to check AXI read/write the same address region.
SPI_CLOSE_AXI_INF_EN

Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data